The invention relates generally to semiconductor-on-insulator (SOI) devices and methods for forming the same and, more particularly to controlling floating body effects and contact resistance within an SOI device.
Traditional semiconductor-on-insulator (SOI) integrated circuits typically have a silicon substrate having a buried oxide (BOX) layer disposed thereon. A semiconductor active layer, typically made from silicon, is disposed on the BOX layer. Within the active layer, active devices, such as transistors, are formed in active regions. The size and placement of the active regions are defined by isolation regions. As a result of this arrangement, the active devices are isolated from the substrate by the BOX layer. More specifically, a body region of each SOI transistor does not have body contacts and is therefore xe2x80x9cfloating.xe2x80x9d
SOI chips offer potential advantages over bulk chips for the fabrication of high performance integrated circuits for digital circuitry. Such digital circuitry is typically made from partially-depleted metal oxide semiconductor field effect transistors (MOSFETs). In such circuits, dielectric isolation and reduction of parasitic capacitance improve circuit performance, and virtually eliminate latch-up in CMOS circuits. In addition, circuit layout in SOI can be greatly simplified and the packing density greatly increased.
However, devices formed from SOI materials typically exhibit parasitic effects due to the presence of the floating body (i.e., xe2x80x9cfloating body effectsxe2x80x9d). These floating body effects may result in undesirable performance in SOI devices. Therefore, it will be appreciated that a need exists for SOI MOSFETs having reduced floating body effects.
According to one aspect of the invention, the invention is a method of forming a semiconductor-on-insulator (SOI) device. The method includes the steps of providing an SOI wafer having a semiconductor active layer, a semiconductor substrate and a buried insulator layer disposed therebetween; defining an active region in the active layer; forming a source, a drain and body in the active region, at least one of the source and the drain forming a hyperabrupt junction with the body; forming a gate disposed on the body such that the source, drain, body and gate are operatively arranged to form a transistor; and forming a silicide region in the at least one of the source and drain forming the hyperabrupt junction with the body, the silicide region having a generally vertical interface, the generally vertical interface being laterally spaced apart from the hyperabrupt junction by about 60 xc3x85 to about 150 xc3x85.
According to another aspect of the invention, the invention is a method of forming a semiconductor-on-insulator (SOI) device. The method includes the steps of providing an SOI wafer having a semiconductor active layer, a semiconductor substrate and a buried insulator layer disposed therebetween; defining an active region in the active layer; forming a source, a drain and body in the active region, the source and the drain forming respective hyperabrupt junctions with the body, the hyperabrupt junctions being formed by a solid phase epitaxy (SPE) process, the SPE process including amorphizing the at least one of the source and the drain, implanting dopant ion species and recrystalizing at temperature of less than 700xc2x0 C.; forming a gate disposed on the body such that the source, drain, body and gate are operatively arranged to form a transistor; and forming a silicide region in each of the source and the drain, the silicide regions being spaced from the respective hyperabrupt junctions by a lateral distance of less than about 100 xc3x85.
These and further features of the present invention will be apparent with reference to the following description and drawings, wherein:
FIG. 1 is a cross-sectional view of a semiconductor-on-insulator (SOI) device in accordance with the present invention;
FIG. 1A is an enlarged, partial view of the SOI device of FIG. 1;
FIG. 2 is a flow chart of a method of making the SOI device of FIG. 1; and
FIGS. 3-9 are cross-sectional views of SOI in various stages of fabrication.